diff options
| author | Robert Richter <rrichter@cavium.com> | 2015-09-21 22:58:37 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2015-09-29 10:10:53 +0200 |
| commit | 67510ccafb9d69e79079b5cd6c9959025bc02061 (patch) | |
| tree | abd1aadd8cac07a1fc00f8b0b103001212c0f984 /drivers/irqchip/irq-gic-common.h | |
| parent | irqchip/gicv3-its: Read typer register outside the loop (diff) | |
| download | linux-67510ccafb9d69e79079b5cd6c9959025bc02061.tar.xz linux-67510ccafb9d69e79079b5cd6c9959025bc02061.zip | |
irqchip/gicv3-its: Add HW revision detection and configuration
Some GIC revisions require an individual configuration to esp. add
workarounds for HW bugs. This patch implements generic code to parse
the hw revision provided by an IIDR register value and runs specific
code if hw matches. A function is added that reads the IIDR registers
for ITS (GITS_IIDR) and then goes through a list of init functions to
be called for specific versions. Same could be done for GICV3
(GICD_IIDR), but there are no users yet for it.
The patch is needed to implement workarounds for HW errata in Cavium's
ThunderX GICV3 ITS.
Signed-off-by: Robert Richter <rrichter@cavium.com>
Reviewed-by: Marc Zygnier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1442869119-1814-5-git-send-email-rric@kernel.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/irqchip/irq-gic-common.h')
| -rw-r--r-- | drivers/irqchip/irq-gic-common.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index 35a9884778bd..fff697db8e22 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -20,10 +20,19 @@ #include <linux/of.h> #include <linux/irqdomain.h> +struct gic_quirk { + const char *desc; + void (*init)(void *data); + u32 iidr; + u32 mask; +}; + int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)); void gic_dist_config(void __iomem *base, int gic_irqs, void (*sync_access)(void)); void gic_cpu_config(void __iomem *base, void (*sync_access)(void)); +void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, + void *data); #endif /* _IRQ_GIC_COMMON_H */ |