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author | Shenming Lu <lushenming@huawei.com> | 2020-11-28 15:18:56 +0100 |
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committer | Marc Zyngier <maz@kernel.org> | 2020-12-11 15:47:10 +0100 |
commit | 0b39498230ae53e6af981141be99f4c7d5144de6 (patch) | |
tree | 3f0629ad35d303ffedf4b195ececfac9b230cff6 /drivers/irqchip/irq-gic-v3-its.c | |
parent | irqchip/alpine-msi: Fix freeing of interrupts on allocation error path (diff) | |
download | linux-0b39498230ae53e6af981141be99f4c7d5144de6.tar.xz linux-0b39498230ae53e6af981141be99f4c7d5144de6.zip |
irqchip/gic-v4.1: Reduce the delay when polling GICR_VPENDBASER.Dirty
The 10us delay of the poll on the GICR_VPENDBASER.Dirty bit is too
high, which might greatly affect the total scheduling latency of a
vCPU in our measurement. So we reduce it to 1 to lessen the impact.
Signed-off-by: Shenming Lu <lushenming@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201128141857.983-2-lushenming@huawei.com
Diffstat (limited to '')
-rw-r--r-- | drivers/irqchip/irq-gic-v3-its.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 4069c215328b..d74ef418e386 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3808,7 +3808,7 @@ static void its_wait_vpt_parse_complete(void) WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER, val, !(val & GICR_VPENDBASER_Dirty), - 10, 500)); + 1, 500)); } static void its_vpe_schedule(struct its_vpe *vpe) |