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authorThomas Gleixner <tglx@linutronix.de>2018-08-06 12:45:42 +0200
committerThomas Gleixner <tglx@linutronix.de>2018-08-06 12:45:42 +0200
commit9e90c7985229430428dc9ba0ec7fe422901b456d (patch)
treecae2072feba8cc433a32d96568bbcf36070bd6e5 /drivers/irqchip/irq-ls-scfg-msi.c
parentgenirq/irqchip: Remove MULTI_IRQ_HANDLER as it's now obselete (diff)
parentirqchip/gic-v3-its: Make its_lock a raw_spin_lock_t (diff)
downloadlinux-9e90c7985229430428dc9ba0ec7fe422901b456d.tar.xz
linux-9e90c7985229430428dc9ba0ec7fe422901b456d.zip
Merge tag 'irqchip-4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier: - GICv3 ITS LPI allocation revamp - GICv3 support for hypervisor-enforced LPI range - GICv3 ITS conversion to raw spinlock
Diffstat (limited to 'drivers/irqchip/irq-ls-scfg-msi.c')
-rw-r--r--drivers/irqchip/irq-ls-scfg-msi.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index 1ec3bfe56693..c671b3212010 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -93,8 +93,12 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
msg->address_lo = lower_32_bits(msi_data->msiir_addr);
msg->data = data->hwirq;
- if (msi_affinity_flag)
- msg->data |= cpumask_first(data->common->affinity);
+ if (msi_affinity_flag) {
+ const struct cpumask *mask;
+
+ mask = irq_data_get_effective_affinity_mask(data);
+ msg->data |= cpumask_first(mask);
+ }
iommu_dma_map_msi_msg(data->irq, msg);
}
@@ -121,7 +125,7 @@ static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
return -EINVAL;
}
- cpumask_copy(irq_data->common->affinity, mask);
+ irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));
return IRQ_SET_MASK_OK;
}