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| author | David S. Miller <davem@davemloft.net> | 2014-01-06 23:37:45 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2014-01-06 23:37:45 +0100 |
| commit | 56a4342dfe3145cd66f766adccb28fd9b571606d (patch) | |
| tree | d1593764488ff8cbb0b83cb9ae35fd968bf81760 /drivers/irqchip/irq-renesas-intc-irqpin.c | |
| parent | net_sched: act: action flushing missaccounting (diff) | |
| parent | bridge: use spin_lock_bh() in br_multicast_set_hash_max (diff) | |
| download | linux-56a4342dfe3145cd66f766adccb28fd9b571606d.tar.xz linux-56a4342dfe3145cd66f766adccb28fd9b571606d.zip | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
drivers/net/ethernet/qlogic/qlcnic/qlcnic_sriov_pf.c
net/ipv6/ip6_tunnel.c
net/ipv6/ip6_vti.c
ipv6 tunnel statistic bug fixes conflicting with consolidation into
generic sw per-cpu net stats.
qlogic conflict between queue counting bug fix and the addition
of multiple MAC address support.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/irqchip/irq-renesas-intc-irqpin.c')
| -rw-r--r-- | drivers/irqchip/irq-renesas-intc-irqpin.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 82cec63a9011..3ee78f02e5d7 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, int irq, int do_mask) { - int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ - int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ + /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ + int bitfield_width = 4; + int shift = 32 - (irq + 1) * bitfield_width; intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, shift, bitfield_width, @@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) { + /* The SENSE register is assumed to be 32-bit. */ int bitfield_width = p->config.sense_bitfield_width; - int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ + int shift = 32 - (irq + 1) * bitfield_width; dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); |