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authorLorenzo Pieralisi <lpieralisi@kernel.org>2023-10-06 14:59:25 +0200
committerMarc Zyngier <maz@kernel.org>2023-10-07 13:47:12 +0200
commit5e5c636c69bdba04033161bbb111fbb6f1f6661e (patch)
treefa77601ec8420789b2ff94fb65f817e03b031e24 /drivers/irqchip
parentdt-bindings: interrupt-controller: renesas,irqc: Add r8a779f0 support (diff)
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dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property
The GIC v3 specifications allow redistributors and ITSes interconnect ports used to access memory to be wired up in a way that makes the respective initiators/memory observers non-coherent. Add the standard dma-noncoherent property to the GICv3 bindings to allow firmware to describe the redistributors/ITSes components and interconnect ports behaviour in system designs where the redistributors and ITSes are not coherent with the CPU. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231006125929.48591-2-lpieralisi@kernel.org
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