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authorHans Verkuil <hans.verkuil@cisco.com>2013-03-11 07:47:25 +0100
committerMauro Carvalho Chehab <mchehab@redhat.com>2013-03-24 16:10:18 +0100
commit1589037f8716a605a36ee6dda6f7cdd4d043522b (patch)
tree00f6593d07cea0e5879ebb70c0242add78966134 /drivers/media/i2c/saa7115.c
parent[media] saa7115: improve querystd handling for the saa7115 (diff)
downloadlinux-1589037f8716a605a36ee6dda6f7cdd4d043522b.tar.xz
linux-1589037f8716a605a36ee6dda6f7cdd4d043522b.zip
[media] saa7115: add support for double-rate ASCLK
Some devices expect a double rate ASCLK. Add a flag to let the driver know through the s_crystal_freq call. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/i2c/saa7115.c')
-rw-r--r--drivers/media/i2c/saa7115.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/media/i2c/saa7115.c b/drivers/media/i2c/saa7115.c
index cdff1f6e8546..52c717d977c9 100644
--- a/drivers/media/i2c/saa7115.c
+++ b/drivers/media/i2c/saa7115.c
@@ -83,9 +83,10 @@ struct saa711x_state {
u32 ident;
u32 audclk_freq;
u32 crystal_freq;
- u8 ucgc;
+ bool ucgc;
u8 cgcdiv;
- u8 apll;
+ bool apll;
+ bool double_asclk;
};
static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
@@ -732,8 +733,12 @@ static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
if (state->apll)
acc |= 0x08;
+ if (state->double_asclk) {
+ acpf <<= 1;
+ acni <<= 1;
+ }
saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
- saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
+ saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
@@ -1302,9 +1307,10 @@ static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
return -EINVAL;
state->crystal_freq = freq;
+ state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;
state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
- state->ucgc = (flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;
- state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;
+ state->ucgc = flags & SAA7115_FREQ_FL_UCGC;
+ state->apll = flags & SAA7115_FREQ_FL_APLL;
saa711x_s_clock_freq(sd, state->audclk_freq);
return 0;
}