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author | Hans Verkuil <hverkuil-cisco@xs4all.nl> | 2018-11-08 10:51:51 +0100 |
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committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-11-23 12:20:55 +0100 |
commit | 2912289a518077ddb8214e05336700148e97e235 (patch) | |
tree | 065f7a5bffa52cecfc1588bc223ba9d3124ebd4f /drivers/media/i2c/tc358743.c | |
parent | media: vim2m: use cancel_delayed_work_sync instead of flush_schedule_work (diff) | |
download | linux-2912289a518077ddb8214e05336700148e97e235.tar.xz linux-2912289a518077ddb8214e05336700148e97e235.zip |
media: adv*/tc358743/ths8200: fill in min width/height/pixelclock
The v4l2_dv_timings_cap struct is used to do sanity checks when setting and
enumerating DV timings, ensuring that only valid timings as per the HW
capabilities are allowed.
However, many drivers just filled in 0 for the minimum width, height or
pixelclock frequency. This can cause timings with e.g. 0 as width and height
to be accepted, which will in turn lead to a potential division by zero.
Fill in proper values are minimum boundaries. 640x350 was chosen since it is
the smallest resolution in v4l2-dv-timings.h. Same for 13 MHz as the lowest
pixelclock frequency (it's slightly below the minimum of 13.5 MHz in the
v4l2-dv-timings.h header).
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Diffstat (limited to 'drivers/media/i2c/tc358743.c')
-rw-r--r-- | drivers/media/i2c/tc358743.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c index 41d470d9ca94..00dc930e049f 100644 --- a/drivers/media/i2c/tc358743.c +++ b/drivers/media/i2c/tc358743.c @@ -59,7 +59,7 @@ static const struct v4l2_dv_timings_cap tc358743_timings_cap = { /* keep this initialization for compatibility with GCC < 4.4.6 */ .reserved = { 0 }, /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */ - V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000, + V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000, V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT, V4L2_DV_BT_CAP_PROGRESSIVE | |