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authorSakari Ailus <sakari.ailus@linux.intel.com>2020-08-04 12:58:30 +0200
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-12-07 15:58:01 +0100
commitd7172c0ebc06b6a363db96fd2fcbd1008f307e4c (patch)
tree89c582affe5fd91c6cd28693188a7fad723dd0e9 /drivers/media
parentmedia: ccs-pll: Add support flexible OP PLL pixel clock divider (diff)
downloadlinux-d7172c0ebc06b6a363db96fd2fcbd1008f307e4c.tar.xz
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media: ccs-pll: Add sanity checks
Add sanity checks for fields that could cause division by zero. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/i2c/ccs-pll.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index e3a6493fd601..420d2c4d7b2c 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -421,6 +421,15 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->vt_lanes = 1;
}
+ if (!pll->op_lanes || !pll->vt_lanes || !pll->bits_per_pixel ||
+ !pll->ext_clk_freq_hz || !pll->link_freq || !pll->scale_m ||
+ !op_lim_fr->min_pll_ip_clk_freq_hz ||
+ !op_lim_fr->max_pll_ip_clk_freq_hz ||
+ !op_lim_fr->min_pll_op_clk_freq_hz ||
+ !op_lim_fr->max_pll_op_clk_freq_hz ||
+ !op_lim_bk->max_sys_clk_div || !op_lim_fr->max_pll_multiplier)
+ return -EINVAL;
+
/*
* Make sure op_pix_clk_div will be integer --- unless flexible
* op_pix_clk_div is supported