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authorThierry Reding <treding@nvidia.com>2014-11-07 16:10:41 +0100
committerThierry Reding <treding@nvidia.com>2015-05-04 12:54:23 +0200
commit242b1d713386e8e2fd7f62cc1ed4681a12290848 (patch)
treee91adedcd99c0700c64e53bc4fa72117e7ade8ef /drivers/memory/tegra/mc.h
parentiommu/tegra-smmu: Add debugfs support (diff)
downloadlinux-242b1d713386e8e2fd7f62cc1ed4681a12290848.tar.xz
linux-242b1d713386e8e2fd7f62cc1ed4681a12290848.zip
memory: tegra: Add Tegra132 support
The memory controller on Tegra132 is very similar to the one found on Tegra124. But the Denver CPUs don't have an outer cache, so dcache maintenance is done slightly differently. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra/mc.h')
-rw-r--r--drivers/memory/tegra/mc.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index d5d21147fc77..b7361b0a6696 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -37,4 +37,8 @@ extern const struct tegra_mc_soc tegra114_mc_soc;
extern const struct tegra_mc_soc tegra124_mc_soc;
#endif
+#ifdef CONFIG_ARCH_TEGRA_132_SOC
+extern const struct tegra_mc_soc tegra132_mc_soc;
+#endif
+
#endif /* MEMORY_TEGRA_MC_H */