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| author | Thierry Reding <treding@nvidia.com> | 2017-10-12 16:29:19 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-15 10:12:32 +0100 |
| commit | 2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8 (patch) | |
| tree | 2f0e111f2fb5f4797a8bce773f122053278c5ca2 /drivers/memory/tegra/tegra30.c | |
| parent | memory: tegra: Add Tegra186 support (diff) | |
| download | linux-2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8.tar.xz linux-2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8.zip | |
memory: tegra: Create SMMU display groups
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210.
This allows the display controllers on these devices to share the same
IOMMU domain using the standard IOMMU group mechanism.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/memory/tegra/tegra30.c')
| -rw-r--r-- | drivers/memory/tegra/tegra30.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index b44737840e70..d756c837f23e 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -934,11 +934,26 @@ static const struct tegra_smmu_swgroup tegra30_swgroups[] = { { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 }, }; +static const unsigned int tegra30_group_display[] = { + TEGRA_SWGROUP_DC, + TEGRA_SWGROUP_DCB, +}; + +static const struct tegra_smmu_group_soc tegra30_groups[] = { + { + .name = "display", + .swgroups = tegra30_group_display, + .num_swgroups = ARRAY_SIZE(tegra30_group_display), + }, +}; + static const struct tegra_smmu_soc tegra30_smmu_soc = { .clients = tegra30_mc_clients, .num_clients = ARRAY_SIZE(tegra30_mc_clients), .swgroups = tegra30_swgroups, .num_swgroups = ARRAY_SIZE(tegra30_swgroups), + .groups = tegra30_groups, + .num_groups = ARRAY_SIZE(tegra30_groups), .supports_round_robin_arbitration = false, .supports_request_limit = false, .num_tlb_lines = 16, |