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authorSimon Glass <sjg@chromium.org>2013-02-25 23:08:39 +0100
committerSamuel Ortiz <sameo@linux.intel.com>2013-04-05 11:20:13 +0200
commita17d94f0b6e1581391378dcb11c18ddebf6dcf8e (patch)
tree79571b890f194e870f9486a69f5687e2e3c78b7e /drivers/mfd/Kconfig
parentmfd: Add ChromeOS EC I2C driver (diff)
downloadlinux-a17d94f0b6e1581391378dcb11c18ddebf6dcf8e.tar.xz
linux-a17d94f0b6e1581391378dcb11c18ddebf6dcf8e.zip
mfd: Add ChromeOS EC SPI driver
This uses a SPI bus to talk to the ChromeOS EC. The protocol is defined by the EC and is fairly simple, with a length byte, checksum, command byte and version byte (to permit easy creation of new commands). Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/Kconfig')
-rw-r--r--drivers/mfd/Kconfig10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4e54b5b01295..94b45476893e 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -39,6 +39,16 @@ config MFD_CROS_EC_I2C
a checksum. Failing accesses will be retried three times to
improve reliability.
+config MFD_CROS_EC_SPI
+ tristate "ChromeOS Embedded Controller (SPI)"
+ depends on MFD_CROS_EC && SPI
+
+ ---help---
+ If you say Y here, you get support for talking to the ChromeOS EC
+ through a SPI bus, using a byte-level protocol. Since the EC's
+ response time cannot be guaranteed, we support ignoring
+ 'pre-amble' bytes before the response actually starts.
+
config MFD_88PM800
tristate "Support Marvell 88PM800"
depends on I2C=y && GENERIC_HARDIRQS