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| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-19 18:02:00 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-19 18:02:00 +0200 |
| commit | 8062b4aafc67376fb55c0438f26410d0563459ec (patch) | |
| tree | bceac42287e7cd3c26bef2e16abfc184d5ac45a2 /drivers/misc/bh1770glc.c | |
| parent | Merge branch 'clk-fixes' into clk-next (diff) | |
| parent | clk: sunxi-ng: Display index when clock registration fails (diff) | |
| download | linux-8062b4aafc67376fb55c0438f26410d0563459ec.tar.xz linux-8062b4aafc67376fb55c0438f26410d0563459ec.zip | |
Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches for 4.12 from Maxime Ripard:
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Display index when clock registration fails
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
clk: sunxi-ng: mult: Support PLL lock detection
clk: sunxi-ng: add support for PRCM CCUs
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: sun5i: Fix mux width for csi clock
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
clk: sunxi-ng: gate: Support common pre-dividers
Diffstat (limited to 'drivers/misc/bh1770glc.c')
0 files changed, 0 insertions, 0 deletions