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| author | Thomas Gleixner <tglx@linutronix.de> | 2015-12-19 12:13:02 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2015-12-19 12:13:02 +0100 |
| commit | ef0bf620e9b81845368b9c72ffdbd6834e424526 (patch) | |
| tree | 7862e4ca1aa61a20f8e11502276b7f8633a39aa4 /drivers/misc/cxl/native.c | |
| parent | genirq: Free irq_desc with rcu (diff) | |
| parent | irqchip/mbigen: Implement the mbigen irq chip operation functions (diff) | |
| download | linux-ef0bf620e9b81845368b9c72ffdbd6834e424526.tar.xz linux-ef0bf620e9b81845368b9c72ffdbd6834e424526.zip | |
Merge branch 'irq/wire-msi-bridge' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull the MSI wire bridge implementation from Marc Zyngier along with
the first user of it. This is infrastructure to support a wired
interrupt to MSI interrupt brigde. The first user is mbigen found in
Hisilicon ARM SoCs.
Diffstat (limited to 'drivers/misc/cxl/native.c')
| -rw-r--r-- | drivers/misc/cxl/native.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c index d2e75c88f4d2..f40909793490 100644 --- a/drivers/misc/cxl/native.c +++ b/drivers/misc/cxl/native.c @@ -497,6 +497,7 @@ static u64 calculate_sr(struct cxl_context *ctx) { u64 sr = 0; + set_endian(sr); if (ctx->master) sr |= CXL_PSL_SR_An_MP; if (mfspr(SPRN_LPCR) & LPCR_TC) @@ -506,7 +507,6 @@ static u64 calculate_sr(struct cxl_context *ctx) sr |= CXL_PSL_SR_An_HV; } else { sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; - set_endian(sr); sr &= ~(CXL_PSL_SR_An_HV); if (!test_tsk_thread_flag(current, TIF_32BIT)) sr |= CXL_PSL_SR_An_SF; |