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| author | Oded Gabbay <ogabbay@kernel.org> | 2021-05-19 13:52:14 +0200 |
|---|---|---|
| committer | Oded Gabbay <ogabbay@kernel.org> | 2021-06-18 14:23:40 +0200 |
| commit | 1242e9f0f45873607f8e6699b4339c81d9f3de73 (patch) | |
| tree | bf5a12f130150236d06924ce5ef55459c7b042b4 /drivers/misc/habanalabs/include/common/hl_boot_if.h | |
| parent | habanalabs: set memory scrubbing to disabled by default (diff) | |
| download | linux-1242e9f0f45873607f8e6699b4339c81d9f3de73.tar.xz linux-1242e9f0f45873607f8e6699b4339c81d9f3de73.zip | |
habanalabs: check running index in eqe control
To harden the event queue mechanism, we add a running index to the
control header of the entry.
The firmware writes the index in each entry and the driver verifies
that the index of the current entry is larger by 1 of the index of
the previous entry.
In case it isn't, the driver will treat the entry as if it wasn't
valid (it won't process it but won't skip it).
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
Diffstat (limited to 'drivers/misc/habanalabs/include/common/hl_boot_if.h')
| -rw-r--r-- | drivers/misc/habanalabs/include/common/hl_boot_if.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/misc/habanalabs/include/common/hl_boot_if.h b/drivers/misc/habanalabs/include/common/hl_boot_if.h index 9266c44d8c6c..6d0c1ddb4304 100644 --- a/drivers/misc/habanalabs/include/common/hl_boot_if.h +++ b/drivers/misc/habanalabs/include/common/hl_boot_if.h @@ -195,7 +195,15 @@ * previleged entity. FW sets this status * bit for host. If this bit is set then * GIC can not be accessed from host. - * Initialized in: armcpd + * Initialized in: linux + * + * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running + * index for each new event sent to host. + * This is used as a method in host to + * identify that the waiting event in + * queue is actually a new event which + * was not served before. + * Initialized in: linux * * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. * This is a main indication that the @@ -226,6 +234,7 @@ #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << 17) #define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << 19) #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN (1 << 20) +#define CPU_BOOT_DEV_STS0_EQ_INDEX_EN (1 << 21) #define CPU_BOOT_DEV_STS0_ENABLED (1 << 31) #define CPU_BOOT_DEV_STS1_ENABLED (1 << 31) |