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authorShawn Lin <shawn.lin@rock-chips.com>2018-04-05 12:31:42 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2018-05-02 15:08:38 +0200
commitd39b1b2abf9fcae3001b868186faa1ae889aecf5 (patch)
treebb81f0649d23b613675b4db4337967423a0e69c1 /drivers/mmc/host/dw_mmc-rockchip.c
parentmmc: sdhci-cadence: send tune request twice to work around errata (diff)
downloadlinux-d39b1b2abf9fcae3001b868186faa1ae889aecf5.tar.xz
linux-d39b1b2abf9fcae3001b868186faa1ae889aecf5.zip
mmc: dw_mmc: fix misleading comment in dw_mci_rk3288_set_ios
DDR52 with 8-bit mode should be handled in a different way when requesting ciu_clk. However DDR50 is used for SDMMC/SDIO and could never be possible with 8-bit mode. It's trival but misleading. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/dw_mmc-rockchip.c')
-rw-r--r--drivers/mmc/host/dw_mmc-rockchip.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
index 40d7de2eea12..8c86a800a8fd 100644
--- a/drivers/mmc/host/dw_mmc-rockchip.c
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
@@ -44,9 +44,8 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
* bus_hz = cclkin / RK3288_CLKGEN_DIV
* ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
*
- * Note: div can only be 0 or 1
- * if DDR50 8bit mode(only emmc work in 8bit mode),
- * div must be set 1
+ * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
+ * DDR52 8-bit mode.
*/
if (ios->bus_width == MMC_BUS_WIDTH_8 &&
ios->timing == MMC_TIMING_MMC_DDR52)