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authorShawn Lin <shawn.lin@rock-chips.com>2017-02-17 03:59:52 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2017-04-24 21:41:06 +0200
commitbc2dcc1a2a5e3e796b71f742d6d241ba0523739b (patch)
tree35d6910c3235562cad4f1c417321034695e5bdb7 /drivers/mmc/host/dw_mmc.c
parentmmc: dw_mmc: move mci_send_cmd forward to avoid declaration (diff)
downloadlinux-bc2dcc1a2a5e3e796b71f742d6d241ba0523739b.tar.xz
linux-bc2dcc1a2a5e3e796b71f742d6d241ba0523739b.zip
mmc: dw_mmc: improve dw_mci_reset a bit
Too much condition iteration makes the code less readable. Slightly improve it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc/host/dw_mmc.c')
-rw-r--r--drivers/mmc/host/dw_mmc.c38
1 files changed, 20 insertions, 18 deletions
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 0c641fb0fe59..d0f0f658e741 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1699,6 +1699,7 @@ static bool dw_mci_reset(struct dw_mci *host)
{
u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
bool ret = false;
+ u32 status = 0;
/*
* Resetting generates a block interrupt, hence setting
@@ -1714,29 +1715,30 @@ static bool dw_mci_reset(struct dw_mci *host)
if (dw_mci_ctrl_reset(host, flags)) {
/*
- * In all cases we clear the RAWINTS register to clear any
- * interrupts.
+ * In all cases we clear the RAWINTS
+ * register to clear any interrupts.
*/
mci_writel(host, RINTSTS, 0xFFFFFFFF);
- /* if using dma we wait for dma_req to clear */
- if (host->use_dma) {
- u32 status;
-
- if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
- status,
- !(status & SDMMC_STATUS_DMA_REQ),
- 1, 500 * USEC_PER_MSEC)) {
- dev_err(host->dev,
- "%s: Timeout waiting for dma_req to clear during reset\n",
- __func__);
- goto ciu_out;
- }
+ if (!host->use_dma) {
+ ret = true;
+ goto ciu_out;
+ }
- /* when using DMA next we reset the fifo again */
- if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
- goto ciu_out;
+ /* Wait for dma_req to be cleared */
+ if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
+ status,
+ !(status & SDMMC_STATUS_DMA_REQ),
+ 1, 500 * USEC_PER_MSEC)) {
+ dev_err(host->dev,
+ "%s: Timeout waiting for dma_req to be cleared\n",
+ __func__);
+ goto ciu_out;
}
+
+ /* when using DMA next we reset the fifo again */
+ if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
+ goto ciu_out;
} else {
/* if the controller reset bit did clear, then set clock regs */
if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {