diff options
| author | Zhangfei Gao <zgao6@marvell.com> | 2010-08-20 20:02:36 +0200 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2010-10-23 15:11:14 +0200 |
| commit | c4687d5f601be3f928b815b46964f7426c31aec7 (patch) | |
| tree | b58c75fd2e7615f6e34637665633b55f02f2d171 /drivers/mmc/host | |
| parent | mmc: SDHC 3.0: support 10-bit divided clock mode (diff) | |
| download | linux-c4687d5f601be3f928b815b46964f7426c31aec7.tar.xz linux-c4687d5f601be3f928b815b46964f7426c31aec7.zip | |
mmc: SDHC 3.0: Base clock frequency change in spec 3.0
SDHC Spec 3.0: Capabilities Register bits[15-08] are Base Clock Frequency
1.0/2.0: Capabilities Register bits[13-08] are Base Clock Frequency
Signed-off-by: Zhangfei Gao <zgao6@marvell.com>
Cc: David Vrabel <david.vrabel@csr.com>
Cc: Matt Fleming <matt@console-pimps.org>
Cc: Michal Miroslaw <mirqus@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc/host')
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 9 | ||||
| -rw-r--r-- | drivers/mmc/host/sdhci.h | 1 |
2 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 4432fec7467a..ac8b12b18fa4 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1794,8 +1794,13 @@ int sdhci_add_host(struct sdhci_host *host) mmc_dev(host->mmc)->dma_mask = &host->dma_mask; } - host->max_clk = - (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + if (host->version >= SDHCI_SPEC_300) + host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) + >> SDHCI_CLOCK_BASE_SHIFT; + else + host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) + >> SDHCI_CLOCK_BASE_SHIFT; + host->max_clk *= 1000000; if (host->max_clk == 0 || host->quirks & SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 950d4fd90072..ae28a310a6a1 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -144,6 +144,7 @@ #define SDHCI_TIMEOUT_CLK_SHIFT 0 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 +#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 #define SDHCI_CLOCK_BASE_SHIFT 8 #define SDHCI_MAX_BLOCK_MASK 0x00030000 #define SDHCI_MAX_BLOCK_SHIFT 16 |