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authorChaotian Jing <chaotian.jing@mediatek.com>2015-10-27 07:24:26 +0100
committerUlf Hansson <ulf.hansson@linaro.org>2015-10-27 10:21:16 +0100
commitc9b5061e7728da1f7192ecaf3ffab4a7300920dc (patch)
tree85a1dce88ee4a767aff4219c41e474699097fd4a /drivers/mmc
parentmmc: mediatek: fix got GPD checksum error interrupt when data transfer (diff)
downloadlinux-c9b5061e7728da1f7192ecaf3ffab4a7300920dc.tar.xz
linux-c9b5061e7728da1f7192ecaf3ffab4a7300920dc.zip
mmc: mediatek: add implement of ops->hw_reset()
add implement of ops->hw_reset() for eMMC Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/mtk-sd.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 385816375614..562764430881 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -64,6 +64,7 @@
#define SDC_RESP2 0x48
#define SDC_RESP3 0x4c
#define SDC_BLK_NUM 0x50
+#define EMMC_IOCON 0x7c
#define SDC_ACMD_RESP 0x80
#define MSDC_DMA_SA 0x90
#define MSDC_DMA_CTRL 0x98
@@ -1209,6 +1210,15 @@ end:
pm_runtime_put_autosuspend(host->dev);
}
+static void msdc_hw_reset(struct mmc_host *mmc)
+{
+ struct msdc_host *host = mmc_priv(mmc);
+
+ sdr_set_bits(host->base + EMMC_IOCON, 1);
+ udelay(10); /* 10us is enough */
+ sdr_clr_bits(host->base + EMMC_IOCON, 1);
+}
+
static struct mmc_host_ops mt_msdc_ops = {
.post_req = msdc_post_req,
.pre_req = msdc_pre_req,
@@ -1216,6 +1226,7 @@ static struct mmc_host_ops mt_msdc_ops = {
.set_ios = msdc_ops_set_ios,
.start_signal_voltage_switch = msdc_ops_switch_volt,
.card_busy = msdc_card_busy,
+ .hw_reset = msdc_hw_reset,
};
static int msdc_drv_probe(struct platform_device *pdev)