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authorJerome Brunet <jbrunet@baylibre.com>2017-08-21 18:02:47 +0200
committerUlf Hansson <ulf.hansson@linaro.org>2017-08-30 15:03:41 +0200
commit130b4bd8f94889e092b8d2fc3c3fe2b483c749a8 (patch)
tree081c22bd05077cce310273c4092294547df35dfc /drivers/mmc
parentmmc: meson-gx: fix mux mask definition (diff)
downloadlinux-130b4bd8f94889e092b8d2fc3c3fe2b483c749a8.tar.xz
linux-130b4bd8f94889e092b8d2fc3c3fe2b483c749a8.zip
mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag
Remove CLK_DIVIDER_ALLOW_ZERO. This flag means that a 1 based divider with a 0 value will behave as a bypass clock The mmc divider does not behave like this, a 0 value disables the clock Remove this flag so CCF never allows a 0 value on this clock Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/meson-gx-mmc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index 4217287923d4..d480a8052a06 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -389,7 +389,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
host->cfg_div.width = __builtin_popcountl(CLK_DIV_MASK);
host->cfg_div.hw.init = &init;
host->cfg_div.flags = CLK_DIVIDER_ONE_BASED |
- CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ALLOW_ZERO;
+ CLK_DIVIDER_ROUND_CLOSEST;
host->cfg_div_clk = devm_clk_register(host->dev, &host->cfg_div.hw);
if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))