diff options
| author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2013-06-13 16:41:28 +0200 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2013-07-05 18:46:28 +0200 |
| commit | 599115686d8f62999a871f7d7ee87de3b939b258 (patch) | |
| tree | 2017d330b0aa6f454b53a44b466266ae5c5b57a2 /drivers/mmc | |
| parent | mmc: dw_mmc-pltfm: add Rockchip variant (diff) | |
| download | linux-599115686d8f62999a871f7d7ee87de3b939b258.tar.xz linux-599115686d8f62999a871f7d7ee87de3b939b258.zip | |
mmc: sdhci: fix ctrl_2 on super-speed selection
This patch fixes the HC ctrl_2 programming where, in case of
SDR104 and HS200, we have to write 100b in the the UHS Mode
bits. We wrote 101b that is reserved from Arasan Specs.
Reported-by: Youssef Triki <youssef.triki@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 9bd6ab203843..3ad3973bdb33 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1543,16 +1543,15 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); /* Select Bus Speed Mode for host */ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; - if (ios->timing == MMC_TIMING_MMC_HS200) - ctrl_2 |= SDHCI_CTRL_HS_SDR200; + if ((ios->timing == MMC_TIMING_MMC_HS200) || + (ios->timing == MMC_TIMING_UHS_SDR104)) + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; else if (ios->timing == MMC_TIMING_UHS_SDR12) ctrl_2 |= SDHCI_CTRL_UHS_SDR12; else if (ios->timing == MMC_TIMING_UHS_SDR25) ctrl_2 |= SDHCI_CTRL_UHS_SDR25; else if (ios->timing == MMC_TIMING_UHS_SDR50) ctrl_2 |= SDHCI_CTRL_UHS_SDR50; - else if (ios->timing == MMC_TIMING_UHS_SDR104) - ctrl_2 |= SDHCI_CTRL_UHS_SDR104; else if (ios->timing == MMC_TIMING_UHS_DDR50) ctrl_2 |= SDHCI_CTRL_UHS_DDR50; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |