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| author | Rafał Miłecki <zajec5@gmail.com> | 2016-04-17 22:52:59 +0200 |
|---|---|---|
| committer | Boris Brezillon <boris.brezillon@free-electrons.com> | 2016-05-05 23:52:03 +0200 |
| commit | d5f304ac6aff1462ddf3c14f48e2b849ab68d5a3 (patch) | |
| tree | d52dc447952063d5e92ce68b6b236bcd8b527924 /drivers/mtd/nand/atmel_nand.c | |
| parent | mtd: nand: davinci: set ECC algorithm explicitly (diff) | |
| download | linux-d5f304ac6aff1462ddf3c14f48e2b849ab68d5a3.tar.xz linux-d5f304ac6aff1462ddf3c14f48e2b849ab68d5a3.zip | |
mtd: nand: atmel: set ECC algorithm explicitly
This is part of process deprecating NAND_ECC_SOFT_BCH (and switching to
enum nand_ecc_algo).
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'drivers/mtd/nand/atmel_nand.c')
| -rw-r--r-- | drivers/mtd/nand/atmel_nand.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index eec8ca739cae..efc8ea250c1d 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1212,6 +1212,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, dev_warn(host->dev, "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n"); nand_chip->ecc.mode = NAND_ECC_SOFT; + nand_chip->ecc.algo = NAND_ECC_HAMMING; return 0; } @@ -1295,6 +1296,7 @@ static int atmel_pmecc_nand_init_params(struct platform_device *pdev, /* page size not handled by HW ECC */ /* switching back to soft ECC */ nand_chip->ecc.mode = NAND_ECC_SOFT; + nand_chip->ecc.algo = NAND_ECC_HAMMING; return 0; } @@ -1613,6 +1615,7 @@ static int atmel_of_init_port(struct atmel_nand_host *host, * even if the nand-ecc-mode property is not defined. */ host->nand_chip.ecc.mode = NAND_ECC_SOFT; + host->nand_chip.ecc.algo = NAND_ECC_HAMMING; return 0; } @@ -1629,6 +1632,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev, dev_err(host->dev, "Can't get I/O resource regs, use software ECC\n"); nand_chip->ecc.mode = NAND_ECC_SOFT; + nand_chip->ecc.algo = NAND_ECC_HAMMING; return 0; } @@ -1661,6 +1665,7 @@ static int atmel_hw_nand_init_params(struct platform_device *pdev, /* page size not handled by HW ECC */ /* switching back to soft ECC */ nand_chip->ecc.mode = NAND_ECC_SOFT; + nand_chip->ecc.algo = NAND_ECC_HAMMING; return 0; } @@ -2160,6 +2165,14 @@ static int atmel_nand_probe(struct platform_device *pdev) sizeof(struct atmel_nand_data)); nand_chip->ecc.mode = host->board.ecc_mode; + /* + * When using software ECC every supported avr32 board means + * Hamming algorithm. If that ever changes we'll need to add + * ecc_algo field to the struct atmel_nand_data. + */ + if (nand_chip->ecc.mode == NAND_ECC_SOFT) + nand_chip->ecc.algo = NAND_ECC_HAMMING; + /* 16-bit bus width */ if (host->board.bus_width_16) nand_chip->options |= NAND_BUSWIDTH_16; |