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author | Takahiro Kuwano <Takahiro.Kuwano@infineon.com> | 2023-07-26 09:52:47 +0200 |
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committer | Tudor Ambarus <tudor.ambarus@linaro.org> | 2023-07-26 11:39:10 +0200 |
commit | d534fd9787d5925d9637752410e3ea92ca7f4cfa (patch) | |
tree | f660f9c009f55019557a27fc3ab7a76c10d3fb09 /drivers/mtd/spi-nor/issi.c | |
parent | mtd: spi-nor: spansion: return method directly (diff) | |
download | linux-d534fd9787d5925d9637752410e3ea92ca7f4cfa.tar.xz linux-d534fd9787d5925d9637752410e3ea92ca7f4cfa.zip |
mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR
Infineon S28Hx (SEMPER Octal) and S25FS256T (SEMPER Nano) support Clear
Program and Erase Failure Flags (CLPEF, 82h) instead of CLSR(30h).
Introduce a new mfr_flag together with the infrastructure to allow
manufacturer private data in the core. With this we remove the need
to have if checks in the code at runtime and instead set the correct
opcodes at probe time. S25Hx (SEMPER QSPI) supports CLSR but it may
be disabled by CFR3x[2] while CLPEF is always available. Therefore,
the mfr_flag is also applied to S25Hx for safety.
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Link: https://lore.kernel.org/r/20230726075257.12985-2-tudor.ambarus@linaro.org
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Diffstat (limited to 'drivers/mtd/spi-nor/issi.c')
-rw-r--r-- | drivers/mtd/spi-nor/issi.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 400e2b42f45a..accdf7aa2bfd 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -29,7 +29,7 @@ static const struct spi_nor_fixups is25lp256_fixups = { .post_bfpt = is25lp256_post_bfpt_fixups, }; -static void pm25lv_nor_late_init(struct spi_nor *nor) +static int pm25lv_nor_late_init(struct spi_nor *nor) { struct spi_nor_erase_map *map = &nor->params->erase_map; int i; @@ -38,6 +38,8 @@ static void pm25lv_nor_late_init(struct spi_nor *nor) for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) if (map->erase_type[i].size == 4096) map->erase_type[i].opcode = SPINOR_OP_BE_4K_PMC; + + return 0; } static const struct spi_nor_fixups pm25lv_nor_fixups = { |