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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2019-10-30 10:01:24 +0100
committerTudor Ambarus <tudor.ambarus@microchip.com>2019-11-11 19:42:53 +0100
commit4c42f63553d79295910f7b4efd5f6dc37fe1a2a5 (patch)
treeaa9df12fc8923982daf8d20263bc363e29c22454 /drivers/mtd/spi-nor
parentmtd: spi-nor: Move condition to avoid a NULL check (diff)
downloadlinux-4c42f63553d79295910f7b4efd5f6dc37fe1a2a5.tar.xz
linux-4c42f63553d79295910f7b4efd5f6dc37fe1a2a5.zip
mtd: spi-nor: Add support for w25q256jw
Add MTD support for w25q256jw SPI NOR chip from Winbond. This chip supports dual/quad I/O mode with 512 blocks of memory organized in 64KB sectors. In addition to this, there is also small 4KB sectors available for flexibility. The device has been validated using Thor96 board. Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Darshak Patel <darshak.patel@einfochips.com> [Mani: cleaned up for upstream] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Diffstat (limited to 'drivers/mtd/spi-nor')
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index fc39db179cbc..159ee7a67c72 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2627,6 +2627,8 @@ static const struct flash_info spi_nor_ids[] = {
{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "w25q256jw", INFO(0xef6019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) },