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authorLinus Walleij <linus.walleij@linaro.org>2019-01-26 14:10:55 +0100
committerMiquel Raynal <miquel.raynal@bootlin.com>2019-02-05 16:56:12 +0100
commit30c72ab142a2d1a49d5fbd4014864cec07cd7a65 (patch)
tree16de98475a7b2435b90374fcb66272e69d365d8e /drivers/mtd
parentmtd: spinand: Add support for GigaDevice GD5F1GQ4UExxG (diff)
downloadlinux-30c72ab142a2d1a49d5fbd4014864cec07cd7a65.tar.xz
linux-30c72ab142a2d1a49d5fbd4014864cec07cd7a65.zip
mtd: rawnand: fsmc: Reset NAND timings on resume()
When we go through a suspend/resume cycle the NAND timings and other settings may have been lost so reset the chip to bring it up in a known working state. The FSMC only supports single CS chips so we only need to call nand_reset(chip, 0). Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r--drivers/mtd/nand/raw/fsmc_nand.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
index 325b4414dccc..9dc0e5b648b1 100644
--- a/drivers/mtd/nand/raw/fsmc_nand.c
+++ b/drivers/mtd/nand/raw/fsmc_nand.c
@@ -1185,6 +1185,7 @@ static int fsmc_nand_resume(struct device *dev)
clk_prepare_enable(host->clk);
if (host->dev_timings)
fsmc_nand_setup(host, host->dev_timings);
+ nand_reset(&host->nand, 0);
}
return 0;