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| author | Matt Burtch <matt@grid-net.com> | 2011-10-17 18:25:45 +0200 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2011-10-25 11:17:44 +0200 |
| commit | 590842f90984f96a3da6d8b59447dfa1d186d01e (patch) | |
| tree | 488f0411e31f9ee130dbf5e72396064793c3919e /drivers/net/atlx | |
| parent | plat-mxc: iomux-v3.h: implicitly enable pull-up/down when that's desired (diff) | |
| download | linux-590842f90984f96a3da6d8b59447dfa1d186d01e.tar.xz linux-590842f90984f96a3da6d8b59447dfa1d186d01e.zip | |
ARM: i.MX28: shift frac value in _CLK_SET_RATE
Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to
reset the clock divider for the SSP0 parent clock, in this case
IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but
when the new frac value is written the value isn't shifted up to write
the correct bit-field. This results in IO0FRAC being set to 0 and
CPUFRAC being corrupted.
This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0
and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1.
Tested on custom i.MX28 board with SSP0 SPI driver.
Signed-off-by: Matt Burtch <matt@grid-net.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'drivers/net/atlx')
0 files changed, 0 insertions, 0 deletions