diff options
| author | Bryan Wu <bryan.wu@analog.com> | 2008-01-30 09:52:22 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-02-03 13:28:47 +0100 |
| commit | 7cc8f38188133e0c278b9f207d63c2c2b4d98236 (patch) | |
| tree | 175e61cd74d95f67394442bb21d4f35038aa1ac4 /drivers/net/bfin_mac.c | |
| parent | EMAC driver: shorten the mdelay value to solve netperf performance issue (diff) | |
| download | linux-7cc8f38188133e0c278b9f207d63c2c2b4d98236.tar.xz linux-7cc8f38188133e0c278b9f207d63c2c2b4d98236.zip | |
EMAC driver: define MDC_CLK=2.5MHz and caculate mdc_div according to SCLK.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bfin_mac.c')
| -rw-r--r-- | drivers/net/bfin_mac.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 4006a5dea654..ee398196ea80 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -412,20 +412,26 @@ static void bf537_adjust_link(struct net_device *dev) spin_unlock_irqrestore(&lp->lock, flags); } +/* MDC = 2.5 MHz */ +#define MDC_CLK 2500000 + static int mii_probe(struct net_device *dev) { struct bf537mac_local *lp = netdev_priv(dev); struct phy_device *phydev = NULL; unsigned short sysctl; int i; + u32 sclk, mdc_div; /* Enable PHY output early */ if (!(bfin_read_VR_CTL() & PHYCLKOE)) bfin_write_VR_CTL(bfin_read_VR_CTL() | PHYCLKOE); - /* MDC = 2.5 MHz */ + sclk = get_sclk(); + mdc_div = ((sclk / MDC_CLK) / 2) - 1; + sysctl = bfin_read_EMAC_SYSCTL(); - sysctl |= SET_MDCDIV(24); + sysctl |= SET_MDCDIV(mdc_div); bfin_write_EMAC_SYSCTL(sysctl); /* search for connect PHY device */ @@ -477,8 +483,10 @@ static int mii_probe(struct net_device *dev) lp->phydev = phydev; printk(KERN_INFO "%s: attached PHY driver [%s] " - "(mii_bus:phy_addr=%s, irq=%d)\n", - DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq); + "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)" + "@sclk=%dMHz)\n", + DRV_NAME, phydev->drv->name, phydev->dev.bus_id, phydev->irq, + MDC_CLK, mdc_div, sclk/1000000); return 0; } |