diff options
| author | Michael Chan <mchan@broadcom.com> | 2008-12-03 09:36:15 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-12-03 09:36:15 +0100 |
| commit | efba01803c8570bab11d0d6188a630231d0ddccf (patch) | |
| tree | ef7971d2aade5064c6049d21db871244194611a9 /drivers/net/bnx2.h | |
| parent | xfrm: Fix kernel panic when flush and dump SPD entries (diff) | |
| download | linux-efba01803c8570bab11d0d6188a630231d0ddccf.tar.xz linux-efba01803c8570bab11d0d6188a630231d0ddccf.zip | |
bnx2: Add workaround to handle missed MSI.
The bnx2 chips do not support per MSI vector masking. On 5706/5708, new MSI
address/data are stored only when the MSI enable bit is toggled. As a result,
SMP affinity no longer works in the latest kernel. A more serious problem is
that the driver will no longer receive interrupts when the MSI receiving CPU
goes offline.
The workaround in this patch only addresses the problem of CPU going offline.
When that happens, the driver's timer function will detect that it is making
no forward progress on pending interrupt events and will recover from it.
Eric Dumazet reported the problem.
We also found that if an interrupt is internally asserted while MSI and INTA
are disabled, the chip will end up in the same state after MSI is re-enabled.
The same workaround is needed for this problem.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Tested-by: Eric Dumazet <dada1@cosmosbay.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.h')
| -rw-r--r-- | drivers/net/bnx2.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 617d95340160..0b032c3c7b61 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -378,6 +378,9 @@ struct l2_fhdr { * pci_config_l definition * offset: 0000 */ +#define BNX2_PCICFG_MSI_CONTROL 0x00000058 +#define BNX2_PCICFG_MSI_CONTROL_ENABLE (1L<<16) + #define BNX2_PCICFG_MISC_CONFIG 0x00000068 #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) @@ -6863,6 +6866,9 @@ struct bnx2 { u8 num_tx_rings; u8 num_rx_rings; + + u32 idle_chk_status_idx; + }; #define REG_RD(bp, offset) \ |