diff options
| author | Michael Chan <mchan@broadcom.com> | 2005-08-26 00:35:24 +0200 |
|---|---|---|
| committer | David S. Miller <davem@sunset.davemloft.net> | 2005-08-30 01:10:34 +0200 |
| commit | cd339a0ed61097d92ce03b6d1042b1e4d58535e7 (patch) | |
| tree | 872886c450910072c3615e8b69a71fb70fa0d42e /drivers/net/bnx2.h | |
| parent | [BNX2]: Fix rtnl deadlock in bnx2_close (diff) | |
| download | linux-cd339a0ed61097d92ce03b6d1042b1e4d58535e7.tar.xz linux-cd339a0ed61097d92ce03b6d1042b1e4d58535e7.zip | |
[BNX2]: speedup serdes linkup
This speeds up link-up time on 5706 SerDes if the link partner does
not autoneg, a rather common scenario in blade servers. Some blade
servers use IPMI for keyboard input and it's important to minimize
link disruptions.
The speedup is achieved by shortening the timer to (HZ / 3) during
the transient period right after initiating a SerDes autoneg. If
autoneg does not complete, parallel detect can be done sooner. After
the transient period is over, the timer goes back to its normal HZ
interval.
As suggested by Jeff Garzik, the timer initialization is moved to
bnx2_init_board() from bnx2_open().
An eeprom bit is also added to allow default forced SerDes speed for
even faster link-up time.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2.h')
| -rw-r--r-- | drivers/net/bnx2.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index 63b94ca0018b..e1fb099acbf2 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -3872,6 +3872,7 @@ struct bnx2 { char *name; int timer_interval; + int current_interval; struct timer_list timer; struct work_struct reset_task; int in_reset_task; @@ -3986,7 +3987,7 @@ struct bnx2 { #define PHY_LOOPBACK 2 u8 serdes_an_pending; -#define SERDES_AN_TIMEOUT (2 * HZ) +#define SERDES_AN_TIMEOUT (HZ / 3) u8 mac_addr[8]; @@ -4172,6 +4173,9 @@ struct fw_info { #define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054 #define BNX2_PORT_HW_CFG_CONFIG 0x00000058 +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 +#define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c |