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authorYaniv Rosner <yanivr@broadcom.com>2009-11-05 18:18:12 +0100
committerDavid S. Miller <davem@davemloft.net>2009-11-06 05:00:35 +0100
commit15ddd2d0ef4849410a2251587b3652fe6a689fda (patch)
tree4964565c9e2f4bf350cc2774f29424c17028eac6 /drivers/net/bnx2x_reg.h
parentbnx2x: Miscellaneous debug print and tabs (diff)
downloadlinux-15ddd2d0ef4849410a2251587b3652fe6a689fda.tar.xz
linux-15ddd2d0ef4849410a2251587b3652fe6a689fda.zip
bnx2x: Enable FC when parallel-detect is used
When parallel detect is used, flow-control is set to the req_fc_auto_adv instead of none. Motive: when 577xx is FC configuration is set to AUTO, while LP speed is set to FORCE mode and FC to force RX/TX, link would come up using parallel detect, and the FC will be set to NONE since FC capabilities were not negotiated, although the LP is setting FC to force RX/TX. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/bnx2x_reg.h')
-rw-r--r--drivers/net/bnx2x_reg.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index b80fde44c85d..4be9bab42f5c 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -4920,6 +4920,8 @@
#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
@@ -4944,6 +4946,8 @@
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
#define MDIO_SERDES_DIGITAL_MISC1 0x18
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000