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authorFelix Fietkau <nbd@nbd.name>2018-07-20 13:58:21 +0200
committerPaul Burton <paul.burton@mips.com>2018-07-20 19:17:04 +0200
commitbc88ad2efd11f29e00a4fd60fcd1887abfe76833 (patch)
tree3ae0c1bc126f6c04b86d260ed18ff1738b666021 /drivers/net/can/xilinx_can.c
parentMIPS: Fix off-by-one in pci_resource_to_user() (diff)
downloadlinux-bc88ad2efd11f29e00a4fd60fcd1887abfe76833.tar.xz
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MIPS: ath79: fix register address in ath79_ddr_wb_flush()
ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets need to be a multiple of 4 in order to access the intended register. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") Patchwork: https://patchwork.linux-mips.org/patch/19912/ Cc: Alban Bedel <albeu@free.fr> Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # 4.2+
Diffstat (limited to 'drivers/net/can/xilinx_can.c')
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