diff options
| author | Arun Ramadoss <arun.ramadoss@microchip.com> | 2022-07-24 11:28:20 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2022-07-27 10:39:17 +0200 |
| commit | b19ac41faa3f9602f245d1ab679f7fa96d388320 (patch) | |
| tree | 8bc5e40bbaa39f091452ff52ee2faeadb9a6f3bf /drivers/net/dsa/microchip/lan937x_reg.h | |
| parent | net: dsa: microchip: lan937x: add support for configuing xMII register (diff) | |
| download | linux-b19ac41faa3f9602f245d1ab679f7fa96d388320.tar.xz linux-b19ac41faa3f9602f245d1ab679f7fa96d388320.zip | |
net: dsa: microchip: apply rgmii tx and rx delay in phylink mac config
This patch read the rgmii tx and rx delay from device tree and stored it
in the ksz_port. It applies the rgmii delay to the xmii tune adjust
register based on the interface selected in phylink mac config. There
are two rgmii port in LAN937x and value to be loaded in the register
vary depends on the port selected.
Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/microchip/lan937x_reg.h')
| -rw-r--r-- | drivers/net/dsa/microchip/lan937x_reg.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index a6cb3ca22dc3..ba4adaddb3ec 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -136,6 +136,12 @@ #define PORT_MII_SEL_EDGE BIT(5) +#define REG_PORT_XMII_CTRL_4 0x0304 +#define REG_PORT_XMII_CTRL_5 0x0306 + +#define PORT_DLL_RESET BIT(15) +#define PORT_TUNE_ADJ GENMASK(13, 7) + /* 4 - MAC */ #define REG_PORT_MAC_CTRL_0 0x0400 #define PORT_CHECK_LENGTH BIT(2) @@ -161,6 +167,18 @@ #define P_PRIO_CTRL REG_PORT_MRI_PRIO_CTRL +/* The port number as per the datasheet */ +#define RGMII_2_PORT_NUM 5 +#define RGMII_1_PORT_NUM 6 + +#define LAN937X_RGMII_2_PORT (RGMII_2_PORT_NUM - 1) +#define LAN937X_RGMII_1_PORT (RGMII_1_PORT_NUM - 1) + +#define RGMII_1_TX_DELAY_2NS 2 +#define RGMII_2_TX_DELAY_2NS 0 +#define RGMII_1_RX_DELAY_2NS 0x1B +#define RGMII_2_RX_DELAY_2NS 0x14 + #define LAN937X_TAG_LEN 2 #endif |