diff options
| author | Bruce Allan <bruce.w.allan@intel.com> | 2010-11-24 07:01:41 +0100 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2010-12-11 07:13:27 +0100 |
| commit | ce54afd16d874ac07378a8bb55d26f7f5b613c0e (patch) | |
| tree | abad7c3150c4acbf3012168d71d611523459694a /drivers/net/e1000e/ich8lan.c | |
| parent | e1000e: 82571 Serdes can fail to get link (diff) | |
| download | linux-ce54afd16d874ac07378a8bb55d26f7f5b613c0e.tar.xz linux-ce54afd16d874ac07378a8bb55d26f7f5b613c0e.zip | |
e1000e: 82577/8/9 mis-configured OEM bits during S0->Sx
The LPLU (Low Power Link Up) and Gigabit Disable bits (a.k.a. OEM bits)
were being configured incorrectly when device goes to D3 state.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/e1000e/ich8lan.c')
| -rw-r--r-- | drivers/net/e1000e/ich8lan.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c index e3374d9a2472..d7fc930d1aa5 100644 --- a/drivers/net/e1000e/ich8lan.c +++ b/drivers/net/e1000e/ich8lan.c @@ -3591,7 +3591,7 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw) ew32(PHY_CTRL, phy_ctrl); if (hw->mac.type >= e1000_pchlan) { - e1000_oem_bits_config_ich8lan(hw, true); + e1000_oem_bits_config_ich8lan(hw, false); ret_val = hw->phy.ops.acquire(hw); if (ret_val) return; |