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author | Auke Kok <auke-jan.h.kok@intel.com> | 2008-02-22 00:11:07 +0100 |
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committer | Jeff Garzik <jeff@garzik.org> | 2008-02-24 06:07:50 +0100 |
commit | 489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3 (patch) | |
tree | e59754bc14703bc13edce3d642d3681a07693385 /drivers/net/e1000e/phy.c | |
parent | e1000e: fix flow control denial of service possibility (diff) | |
download | linux-489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3.tar.xz linux-489815ce224e75c2fcd5ebdfaa740d7f9a4f20d3.zip |
e1000e: fix spelling errors in comments
Fix some spelling errors and inconsistencies in comment blocks.
Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/e1000e/phy.c')
-rw-r--r-- | drivers/net/e1000e/phy.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index fc6fee112f1c..dab3c468a768 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c @@ -121,7 +121,7 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) * @offset: register offset to be read * @data: pointer to the read data * - * Reads the MDI control regsiter in the PHY at offset and stores the + * Reads the MDI control register in the PHY at offset and stores the * information read to data. **/ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) @@ -1172,7 +1172,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) } /** - * e1000e_check_downshift - Checks whether a downshift in speed occured + * e1000e_check_downshift - Checks whether a downshift in speed occurred * @hw: pointer to the HW structure * * Success returns 0, Failure returns 1 @@ -1388,8 +1388,8 @@ s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) * * The automatic gain control (agc) normalizes the amplitude of the * received signal, adjusting for the attenuation produced by the - * cable. By reading the AGC registers, which reperesent the - * cobination of course and fine gain value, the value can be put + * cable. By reading the AGC registers, which represent the + * combination of course and fine gain value, the value can be put * into a lookup table to obtain the approximate cable length * for each channel. **/ @@ -1619,7 +1619,7 @@ s32 e1000e_phy_sw_reset(struct e1000_hw *hw) * Verify the reset block is not blocking us from resetting. Acquire * semaphore (if necessary) and read/set/write the device control reset * bit in the PHY. Wait the appropriate delay time for the device to - * reset and relase the semaphore (if necessary). + * reset and release the semaphore (if necessary). **/ s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) { |