diff options
| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-03-28 00:07:06 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-03-28 19:41:18 +0100 |
| commit | a1ae385df210a9fe272b87683192f2789ddf144e (patch) | |
| tree | 39bd5c50582fbb35215f395b726aa5ac68b4c3f0 /drivers/net/ethernet/cadence | |
| parent | net/macb: clear tx/rx completion flags in ISR (diff) | |
| download | linux-a1ae385df210a9fe272b87683192f2789ddf144e.tar.xz linux-a1ae385df210a9fe272b87683192f2789ddf144e.zip | |
net/macb: force endian_swp_pkt_en to off
The core has a bit for swapping packet data endianism.
Reset default from Cadence is off. Xilinx however, who uses this core on the
Zynq SoCs, opted for on.
Force it to off. This shouldn't change the behaviour for current users of the
macb, but enables usage on Zynq devices.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/cadence')
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.c | 1 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index 3593c2c594a6..2747a7f59528 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1057,6 +1057,7 @@ static void macb_configure_dma(struct macb *bp) dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); dmacfg |= GEM_BF(FBLDO, 16); dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); + dmacfg &= ~GEM_BIT(ENDIA); gem_writel(bp, DMACFG, dmacfg); } } diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 570908b93578..993d70380688 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -173,6 +173,8 @@ /* Bitfields in DMACFG. */ #define GEM_FBLDO_OFFSET 0 #define GEM_FBLDO_SIZE 5 +#define GEM_ENDIA_OFFSET 7 +#define GEM_ENDIA_SIZE 1 #define GEM_RXBMS_OFFSET 8 #define GEM_RXBMS_SIZE 2 #define GEM_TXPBMS_OFFSET 10 |