diff options
| author | Bruce Allan <bruce.w.allan@intel.com> | 2012-12-27 09:32:33 +0100 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2013-01-18 13:55:07 +0100 |
| commit | b67e191307a3f330525265af3e2877a74d557cbf (patch) | |
| tree | b1be965c24cf81c2a244c420427c3937888abb92 /drivers/net/ethernet/intel/e1000e/hw.h | |
| parent | e1000e: Use standard #defines for PCIe Capability ASPM fields (diff) | |
| download | linux-b67e191307a3f330525265af3e2877a74d557cbf.tar.xz linux-b67e191307a3f330525265af3e2877a74d557cbf.zip | |
e1000e: add support for hardware timestamping on some devices
On 82574, 82583, 82579, I217 and I218 add support for hardware time
stamping of all or no Rx packets and Tx packets which have the
SKBTX_HW_TSTAMP flag set. Update the .get_ts_info ethtool operation to
report the supported time stamping modes, and enable and disable hardware
time stamping with the SIOCSHWTSTAMP ioctl.
Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/hw.h')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000e/hw.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h index 81afad5b80f2..8e7e80345a60 100644 --- a/drivers/net/ethernet/intel/e1000e/hw.h +++ b/drivers/net/ethernet/intel/e1000e/hw.h @@ -60,6 +60,7 @@ enum e1e_registers { E1000_EIAC_82574 = 0x000DC, /* Ext. Interrupt Auto Clear - RW */ E1000_IAM = 0x000E0, /* Interrupt Acknowledge Auto Mask */ E1000_IVAR = 0x000E4, /* Interrupt Vector Allocation - RW */ + E1000_FEXTNVM7 = 0x000E4, /* Future Extended NVM 7 - RW */ E1000_EITR_82574_BASE = 0x000E8, /* Interrupt Throttling - RW */ #define E1000_EITR_82574(_n) (E1000_EITR_82574_BASE + (_n << 2)) E1000_LPIC = 0x000FC, /* Low Power Idle Control - RW */ @@ -241,6 +242,15 @@ enum e1e_registers { #define E1000_PCH_RAICC(_n) (E1000_PCH_RAICC_BASE + ((_n) * 4)) #define E1000_CRC_OFFSET E1000_PCH_RAICC_BASE E1000_HICR = 0x08F00, /* Host Interface Control */ + E1000_SYSTIML = 0x0B600, /* System time register Low - RO */ + E1000_SYSTIMH = 0x0B604, /* System time register High - RO */ + E1000_TIMINCA = 0x0B608, /* Increment attributes register - RW */ + E1000_TSYNCTXCTL = 0x0B614, /* Tx Time Sync Control register - RW */ + E1000_TXSTMPL = 0x0B618, /* Tx timestamp value Low - RO */ + E1000_TXSTMPH = 0x0B61C, /* Tx timestamp value High - RO */ + E1000_TSYNCRXCTL = 0x0B620, /* Rx Time Sync Control register - RW */ + E1000_RXSTMPL = 0x0B624, /* Rx timestamp Low - RO */ + E1000_RXSTMPH = 0x0B628, /* Rx timestamp High - RO */ }; #define E1000_MAX_PHY_ADDR 4 |