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author | Alexander Duyck <alexander.h.duyck@intel.com> | 2011-06-11 03:45:03 +0200 |
---|---|---|
committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-07-22 07:55:56 +0200 |
commit | 08c8833b29cfa4343ff132eebc5648b234eb3f85 (patch) | |
tree | 68fac5d690c63d9f83e654b4315e801e73f2eead /drivers/net/ixgbe/ixgbe.h | |
parent | ixgbe: inline the ixgbe_maybe_stop_tx function (diff) | |
download | linux-08c8833b29cfa4343ff132eebc5648b234eb3f85.tar.xz linux-08c8833b29cfa4343ff132eebc5648b234eb3f85.zip |
ixgbe: add structure for containing RX/TX rings to q_vector
This patch adds support for a ring container structure to be used within
the q_vector. The basic idea is to provide a means of separating the RX
and TX rings while maintaining a common structure for their containment.
The advantage to this is that later we should be able to pass this
structure to the update_itr functions without needing to pass individual
rings.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Tested-by: Ross Brattain <ross.b.brattain@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe/ixgbe.h')
-rw-r--r-- | drivers/net/ixgbe/ixgbe.h | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h index 744b64108130..a5ed9fd69fdd 100644 --- a/drivers/net/ixgbe/ixgbe.h +++ b/drivers/net/ixgbe/ixgbe.h @@ -277,6 +277,15 @@ struct ixgbe_ring_feature { int mask; } ____cacheline_internodealigned_in_smp; +struct ixgbe_ring_container { +#if MAX_RX_QUEUES > MAX_TX_QUEUES + DECLARE_BITMAP(idx, MAX_RX_QUEUES); +#else + DECLARE_BITMAP(idx, MAX_TX_QUEUES); +#endif + u8 count; /* total number of rings in vector */ + u8 itr; /* current ITR setting for ring */ +}; #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \ ? 8 : 1) @@ -294,12 +303,7 @@ struct ixgbe_q_vector { int cpu; /* CPU for DCA */ #endif struct napi_struct napi; - DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */ - DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */ - u8 rxr_count; /* Rx ring count assigned to this vector */ - u8 txr_count; /* Tx ring count assigned to this vector */ - u8 tx_itr; - u8 rx_itr; + struct ixgbe_ring_container rx, tx; u32 eitr; cpumask_var_t affinity_mask; char name[IFNAMSIZ + 9]; |