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| author | Emil Tantilov <emil.s.tantilov@intel.com> | 2011-02-26 07:40:11 +0100 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2011-03-08 03:06:06 +0100 |
| commit | a3aeea0ec8d3af854edf7dc983dc8cbe803a43e8 (patch) | |
| tree | 9953d4b01861113a9c81862919cb523e18612ff1 /drivers/net/ixgbe | |
| parent | ixgbe: clear correct counters for flow control on 82599 (diff) | |
| download | linux-a3aeea0ec8d3af854edf7dc983dc8cbe803a43e8.tar.xz linux-a3aeea0ec8d3af854edf7dc983dc8cbe803a43e8.zip | |
ixgbe: Add x540 statistic counter definitions
Add defines to accumulate and display x540 PHY statistic counters on
transmit/receive.
Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Stephen Ko <stephen.s.ko@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ixgbe')
| -rw-r--r-- | drivers/net/ixgbe/ixgbe_common.c | 9 | ||||
| -rw-r--r-- | drivers/net/ixgbe/ixgbe_type.h | 5 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c index 85cc30143738..561f666618e4 100644 --- a/drivers/net/ixgbe/ixgbe_common.c +++ b/drivers/net/ixgbe/ixgbe_common.c @@ -209,6 +209,15 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) } } + if (hw->mac.type == ixgbe_mac_X540) { + if (hw->phy.id == 0) + hw->phy.ops.identify(hw); + hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECL, &i); + hw->phy.ops.read_reg(hw, 0x3, IXGBE_PCRC8ECH, &i); + hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECL, &i); + hw->phy.ops.read_reg(hw, 0x3, IXGBE_LDPCECH, &i); + } + return 0; } diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h index 13a45c7c89d0..76bf21b8a10d 100644 --- a/drivers/net/ixgbe/ixgbe_type.h +++ b/drivers/net/ixgbe/ixgbe_type.h @@ -671,6 +671,11 @@ #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ +#define IXGBE_PCRC8ECL 0x0E810 +#define IXGBE_PCRC8ECH 0x0E811 +#define IXGBE_PCRC8ECH_MASK 0x1F +#define IXGBE_LDPCECL 0x0E820 +#define IXGBE_LDPCECH 0x0E821 /* Management */ #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ |