diff options
| author | Francois Romieu <romieu@fr.zoreil.com> | 2006-09-11 20:10:58 +0200 |
|---|---|---|
| committer | Francois Romieu <romieu@fr.zoreil.com> | 2006-09-11 19:51:47 +0200 |
| commit | b39fe41f481d20c201012e4483e76c203802dda7 (patch) | |
| tree | 06493995b74c1fd2f40561b0f6924d3b863f166f /drivers/net/r8169.c | |
| parent | r8169: the 0x8136 needs a 8 bytes alignment (diff) | |
| download | linux-b39fe41f481d20c201012e4483e76c203802dda7.tar.xz linux-b39fe41f481d20c201012e4483e76c203802dda7.zip | |
r8169: quirk for the 8110sb on arm platform
Inverting the write ordering of the TxDescAddr{High/Low} registers
suffices to trigger a sabbat of PCI errors which make the device
completely dysfunctional. The issue has not been reported on a
different platform.
Switching from MMIO accesses to I/O ones as done in Realtek's
own driver fixes (papers over ?) the bug as well but I am not
thrilled to see everyone pay the I/O price for an obscure bug.
This is the minimal change to handle the issue.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Reported-by: Lennert Buytenhek <buytenh@wantstofly.org>
Diffstat (limited to 'drivers/net/r8169.c')
| -rw-r--r-- | drivers/net/r8169.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 93228c518ae7..805562b8624e 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -1904,10 +1904,15 @@ rtl8169_hw_start(struct net_device *dev) */ RTL_W16(IntrMitigate, 0x0000); - RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK)); + /* + * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh + * register to be written before TxDescAddrLow to work. + * Switching from MMIO to I/O access fixes the issue as well. + */ RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); - RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); + RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK)); RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); + RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); RTL_W8(Cfg9346, Cfg9346_Lock); |