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author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-20 23:49:00 +0200 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-20 23:49:00 +0200 |
commit | ff9144530e9cfe8923e00172e3f8ff83c3b8ff8b (patch) | |
tree | c64a9528dde590b9f3174125ad361f46ee30bba8 /drivers/net/smc91x.h | |
parent | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus (diff) | |
parent | [ARM] 3559/1: S3C2442: core and serial port (diff) | |
download | linux-ff9144530e9cfe8923e00172e3f8ff83c3b8ff8b.tar.xz linux-ff9144530e9cfe8923e00172e3f8ff83c3b8ff8b.zip |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits)
[ARM] 3559/1: S3C2442: core and serial port
[ARM] 3557/1: S3C24XX: centralise and cleanup uart registration
[ARM] 3558/1: SMDK24XX: LED platform devices
[ARM] 3534/1: add spi support to lubbock platform
[ARM] 3554/1: ARM: Fix dyntick locking
[ARM] 3553/1: S3C24XX: earlier print of cpu idcode info
[ARM] 3552/1: S3C24XX: Move VA of GPIO for low-level debug
[ARM] 3551/1: S3C24XX: PM code failes to compile with CONFIG_DCACHE_WRITETHROUGH
[ARM] 3550/1: OSIRIS: fix serial port map for 1:1
[ARM] 3548/1: Fix the ARMv6 CPU id in compressed/head.S
[ARM] 3335/1: Old-abi Thumb sys_syscall broken
[ARM] 3467/1: [3/3] Support for Philips PNX4008 platform: defconfig
[ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support
[ARM] 3465/1: [1/3] Support for Philips PNX4008 platform: headers
[ARM] 3407/1: lpd7x: documetation update
[ARM] 3406/1: lpd7x: compilation fix for smc91x
[ARM] 3405/1: lpd7a40x: CPLD ssp driver
[ARM] 3404/1: lpd7a40x: AMBA CLCD support
[ARM] 3403/1: lpd7a40x: updated default configurations
[ARM] 3402/1: lpd7a40x: serial driver bug fix
...
Diffstat (limited to 'drivers/net/smc91x.h')
-rw-r--r-- | drivers/net/smc91x.h | 44 |
1 files changed, 28 insertions, 16 deletions
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index f72a4f57905a..bf776125ca38 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h @@ -260,15 +260,17 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define RPC_LSA_DEFAULT RPC_LED_TX_RX #define RPC_LSB_DEFAULT RPC_LED_100_10 -#elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404) +#elif defined(CONFIG_MACH_LPD79520) \ + || defined(CONFIG_MACH_LPD7A400) \ + || defined(CONFIG_MACH_LPD7A404) -/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between - * the way that the CPU handles chip selects and the way that the SMC - * chip expects the chip select to operate. Refer to +/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the + * way that the CPU handles chip selects and the way that the SMC chip + * expects the chip select to operate. Refer to * Documentation/arm/Sharp-LH/IOBarrier for details. The read from - * IOBARRIER is a byte as a least-common denominator of possible - * regions to use as the barrier. It would be wasteful to read 32 - * bits from a byte oriented region. + * IOBARRIER is a byte, in order that we read the least-common + * denominator. It would be wasteful to read 32 bits from an 8-bit + * accessible region. * * There is no explicit protection against interrupts intervening * between the writew and the IOBARRIER. In SMC ISR there is a @@ -287,25 +289,35 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg) #define SMC_CAN_USE_16BIT 1 #define SMC_CAN_USE_32BIT 0 #define SMC_NOWAIT 0 -#define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT) +#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) -#define SMC_inw(a,r) readw ((void*) ((a) + (r))) -#define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l) -#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; }) +#define SMC_inw(a,r)\ + ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) +#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) -#define SMC_outsw LPD7A40X_SMC_outsw +#define SMC_insw LPD7_SMC_insw +static inline void LPD7_SMC_insw (unsigned char* a, int r, + unsigned char* p, int l) +{ + unsigned short* ps = (unsigned short*) p; + while (l-- > 0) { + *ps++ = readw (a + r); + LPD7X_IOBARRIER; + } +} -static inline void LPD7A40X_SMC_outsw(unsigned long a, int r, - unsigned char* p, int l) +#define SMC_outsw LPD7_SMC_outsw +static inline void LPD7_SMC_outsw (unsigned char* a, int r, + unsigned char* p, int l) { unsigned short* ps = (unsigned short*) p; while (l-- > 0) { writew (*ps++, a + r); - LPD7A40X_IOBARRIER; + LPD7X_IOBARRIER; } } -#define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER +#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER #define RPC_LSA_DEFAULT RPC_LED_TX_RX #define RPC_LSB_DEFAULT RPC_LED_100_10 |