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| author | Matt Carlson <mcarlson@broadcom.com> | 2010-04-12 08:58:24 +0200 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-04-13 11:25:42 +0200 |
| commit | cea46462681d61a65a208d17206d38739c1ea1b1 (patch) | |
| tree | af5b17960d6871e9dc2b6d104eaadf87730220f5 /drivers/net/tg3.h | |
| parent | net: sk_dst_cache RCUification (diff) | |
| download | linux-cea46462681d61a65a208d17206d38739c1ea1b1.tar.xz linux-cea46462681d61a65a208d17206d38739c1ea1b1.zip | |
tg3: Disable CLKREQ in L2
This patch disables CLKREQ in L2 to workaround a chipset bug.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 5d7f72a2ea01..8a6012ab23ff 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1854,6 +1854,8 @@ #define TG3_PCIE_TLDLPL_PORT 0x00007c00 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 +#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 +#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 /* OTP bit definitions */ #define TG3_OTP_AGCTGT_MASK 0x000000e0 |