diff options
| author | Mohamed Abbas <mohamed.abbas@intel.com> | 2009-05-22 20:01:52 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2009-05-22 20:06:09 +0200 |
| commit | 40cefda9ce11c44a2531d07af812900aa5f3ce9d (patch) | |
| tree | 08b4108aa0c9678bb76450212e0806234134731e /drivers/net/wireless/iwlwifi/iwl-csr.h | |
| parent | iwlcore: Allow skb allocation from tasklet. (diff) | |
| download | linux-40cefda9ce11c44a2531d07af812900aa5f3ce9d.tar.xz linux-40cefda9ce11c44a2531d07af812900aa5f3ce9d.zip | |
iwlcore: Add support for periodic RX interrupt
Periodic RX interrupt needed with ICT interrupt to prevent RX race.
Sending RX interrupt require many steps to be done in the
the device:
1- write interrupt to current index in ICT table.
2- dma RX frame.
3- update RX shared data to indicate last write index.
4- send interrupt.
This could lead to RX race, driver could receive RX interrupt
but the shared data changes does not reflect that.
this could lead to RX race, RX periodic will solve this race
Signed-off-by: Mohamed Abbas <mohamed.abbas@intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
| -rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-csr.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index 34c123ea1d3e..e2fafb828684 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h @@ -100,6 +100,7 @@ #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) +#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) /* Analog phase-lock-loop configuration */ #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) /* @@ -129,12 +130,14 @@ #define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN (0x02000000) #define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME (0x08000000) +#define CSR_INT_PERIODIC_DIS (0x00) +#define CSR_INT_PERIODIC_ENA (0xFF) /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), * acknowledged (reset) by host writing "1" to flagged bits. */ #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ -#define CSR_INT_BIT_DNLD (1 << 28) /* uCode Download */ +#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ |