diff options
| author | Juuso Oikarinen <juuso.oikarinen@nokia.com> | 2009-10-12 14:08:49 +0200 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2009-10-27 21:48:04 +0100 |
| commit | 284134eb6f928f6cdbfe95ab79f8e46233a22c98 (patch) | |
| tree | 53e70a9c2a6597a9896ab014e710972a85858a25 /drivers/net/wireless/wl12xx/wl1271_boot.c | |
| parent | wl1271: Add top-register access functions (diff) | |
| download | linux-284134eb6f928f6cdbfe95ab79f8e46233a22c98.tar.xz linux-284134eb6f928f6cdbfe95ab79f8e46233a22c98.zip | |
wl1271: RefClk configuration
Updated RefClk configuration based on reference sources. Apparently this
change will improve RF performance.
Signed-off-by: Juuso Oikarinen <juuso.oikarinen@nokia.com>
Reviewed-by: Luciano Coelho <luciano.coelho@nokia.com>
Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/wl12xx/wl1271_boot.c')
| -rw-r--r-- | drivers/net/wireless/wl12xx/wl1271_boot.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.c b/drivers/net/wireless/wl12xx/wl1271_boot.c index 1a3084cca9b8..b58657750716 100644 --- a/drivers/net/wireless/wl12xx/wl1271_boot.c +++ b/drivers/net/wireless/wl12xx/wl1271_boot.c @@ -435,13 +435,29 @@ int wl1271_boot(struct wl1271 *wl) int ret = 0; u32 tmp, clk, pause; - if (REF_CLOCK == 0 || REF_CLOCK == 2) - /* ref clk: 19.2/38.4 */ + if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4) + /* ref clk: 19.2/38.4/38.4-XTAL */ clk = 0x3; else if (REF_CLOCK == 1 || REF_CLOCK == 3) /* ref clk: 26/52 */ clk = 0x5; + if (REF_CLOCK != 0) { + u16 val; + /* Set clock type */ + val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE); + val &= FREF_CLK_TYPE_BITS; + val |= CLK_REQ_PRCM; + wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val); + } else { + u16 val; + /* Set clock polarity */ + val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY); + val &= FREF_CLK_POLARITY_BITS; + val |= CLK_REQ_OUTN_SEL; + wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val); + } + wl1271_reg_write32(wl, PLL_PARAMETERS, clk); pause = wl1271_reg_read32(wl, PLL_PARAMETERS); |