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authorJiawen Wu <jiawenwu@trustnetic.com>2023-07-19 11:22:33 +0200
committerDavid S. Miller <davem@davemloft.net>2023-07-23 12:47:07 +0200
commitc7b75bea853daeb64fc831dbf39a6bbabcc402ac (patch)
tree3dea2dd6692a3b02ccecbf63d792c4449dfcc751 /drivers/net
parentdocs: net: clarify the NAPI rules around XDP Tx (diff)
downloadlinux-c7b75bea853daeb64fc831dbf39a6bbabcc402ac.tar.xz
linux-c7b75bea853daeb64fc831dbf39a6bbabcc402ac.zip
net: phy: marvell10g: fix 88x3310 power up
Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY, it sometimes does not take effect immediately. And a read of this register causes the bit not to clear. This will cause mv3310_reset() to time out, which will fail the config initialization. So add a delay before the next access. Fixes: c9cc1c815d36 ("net: phy: marvell10g: place in powersave mode at probe") Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/phy/marvell10g.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 55d9d7acc32e..d4bb90d76881 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev)
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
MV_V2_PORT_CTRL_PWRDOWN);
+ /* Sometimes, the power down bit doesn't clear immediately, and
+ * a read of this register causes the bit not to clear. Delay
+ * 100us to allow the PHY to come out of power down mode before
+ * the next access.
+ */
+ udelay(100);
+
if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
priv->firmware_ver < 0x00030000)
return ret;