Merge branch 'remotes/lorenzo/pci/endpoint'

  - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
    endpoint framework (Wen Yang)

  - Add interface to discover supported endpoint features to replace a
    bitfield that wasn't flexible enough (Kishon Vijay Abraham I)

  - Implement the new supported-feature interface for designware-plat,
    dra7xx, rockchip, cadence (Kishon Vijay Abraham I)

  - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)

  - Add layerscape endpoint mode support (Xiaowei Bao)

* remotes/lorenzo/pci/endpoint:
  misc: pci_endpoint_test: Add the layerscape EP device support
  PCI: layerscape: Add EP mode support
  arm64: dts: Add the PCIE EP node in dts
  dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
  PCI: endpoint: Remove features member in struct pci_epc
  PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
  PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
  PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
  PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
  PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
  PCI: pci-epf-test: Remove setting epf_bar flags in function driver
  PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
  PCI: endpoint: Add helper to get first unreserved BAR
  PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
  PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
  PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
  PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
  PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
  PCI: endpoint: Add new pci_epc_ops to get EPC features
  PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()

1 files changed, 13 insertions, 4 deletions

diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index cee7b4a04fed..932dbd0b34b6 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -68,14 +68,10 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	struct pci_epc *epc = ep->epc;
 	enum pci_barno bar;
 
 	for (bar = BAR_0; bar <= BAR_5; bar++)
 		dw_pcie_ep_reset_bar(pci, bar);
-
-	epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
-	epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
 }
 
 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
@@ -98,9 +94,22 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+static const struct pci_epc_features dw_plat_pcie_epc_features = {
+	.linkup_notifier = false,
+	.msi_capable = true,
+	.msix_capable = true,
+};
+
+static const struct pci_epc_features*
+dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
+{
+	return &dw_plat_pcie_epc_features;
+}
+
 static struct dw_pcie_ep_ops pcie_ep_ops = {
 	.ep_init = dw_plat_pcie_ep_init,
 	.raise_irq = dw_plat_pcie_ep_raise_irq,
+	.get_features = dw_plat_pcie_get_features,
 };
 
 static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,