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authorAlan Douglas <adouglas@cadence.com>2018-06-25 10:30:52 +0200
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2018-07-12 13:44:14 +0200
commitee12c9efe685428ebfae1bf5347b5375f54ce44e (patch)
treefa4547e150a97e7dbf36fb55124f2ef3d9d157fa /drivers/pci/controller/pcie-cadence-ep.c
parentdt-bindings: PCI: cadence: Add DT bindings for optional PHYs (diff)
downloadlinux-ee12c9efe685428ebfae1bf5347b5375f54ce44e.tar.xz
linux-ee12c9efe685428ebfae1bf5347b5375f54ce44e.zip
PCI: cadence: Add Power Management ops for host and EP
These PM ops will enable/disable the optional PHYs if present. The AXI link-down register in the host driver is now cleared in cdns_pci_map_bus() since the link-down bit will be set if the PHY has been disabled. It is not cleared when enabling the PHY, since the link will not yet be up (e.g. when an EP controller is connected back-to-back to the host controller and its PHY is still disabled). Link: http://lkml.kernel.org/r/1529915453-4633-5-git-send-email-adouglas@cadence.com Signed-off-by: Alan Douglas <adouglas@cadence.com> [lorenzo.pieralisi@arm.com: updated commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Diffstat (limited to 'drivers/pci/controller/pcie-cadence-ep.c')
-rw-r--r--drivers/pci/controller/pcie-cadence-ep.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c02f33d8e506..3eabd99a1233 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -555,6 +555,7 @@ static struct platform_driver cdns_pcie_ep_driver = {
.driver = {
.name = "cdns-pcie-ep",
.of_match_table = cdns_pcie_ep_of_match,
+ .pm = &cdns_pcie_pm_ops,
},
.probe = cdns_pcie_ep_probe,
.shutdown = cdns_pcie_ep_shutdown,