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| author | Rick Wertenbroek <rick.wertenbroek@gmail.com> | 2023-04-18 09:46:53 +0200 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2023-06-22 09:36:51 +0200 |
| commit | 21a2960d5ea2e70c15256b73fce1a14999071090 (patch) | |
| tree | 67f009b206abd382924227e5c4703a471a64ea7a /drivers/pci/controller/pcie-rockchip.h | |
| parent | PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked (diff) | |
| download | linux-21a2960d5ea2e70c15256b73fce1a14999071090.tar.xz linux-21a2960d5ea2e70c15256b73fce1a14999071090.zip | |
dt-bindings: PCI: Update the RK3399 example to a valid one
Update the example in the documentation to a valid example.
Address for mem-base was invalid, it pointed to address
0x8000'0000 which is the upper region of the DDR which
is not necessarily populated depending on the board.
This address should point to the base of the memory
window region of the controller which is 0xfa00'0000.
Add missing pinctrl.
Link: https://lore.kernel.org/r/20230418074700.1083505-7-rick.wertenbroek@gmail.com
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'drivers/pci/controller/pcie-rockchip.h')
0 files changed, 0 insertions, 0 deletions