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authorBjorn Helgaas <bhelgaas@google.com>2023-08-29 18:03:55 +0200
committerBjorn Helgaas <bhelgaas@google.com>2023-08-29 18:03:55 +0200
commit663544b5697e8c8a815f3ace8e49d62716d653b8 (patch)
tree536e65c8ce57fc88af110c493fbdd75d0fd44331 /drivers/pci/controller
parentMerge branch 'pci/controller/tegra194' (diff)
parentPCI: vmd: Disable bridge window for domain reset (diff)
downloadlinux-663544b5697e8c8a815f3ace8e49d62716d653b8.tar.xz
linux-663544b5697e8c8a815f3ace8e49d62716d653b8.zip
Merge branch 'pci/controller/vmd'
- Fix disable of bridge windows during domain reset; previously we cleared the base/limit registers, which left the windows enabled (Nirmal Patel) * pci/controller/vmd: PCI: vmd: Disable bridge window for domain reset
Diffstat (limited to 'drivers/pci/controller')
-rw-r--r--drivers/pci/controller/vmd.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c
index e718a816d481..ad56df98b8e6 100644
--- a/drivers/pci/controller/vmd.c
+++ b/drivers/pci/controller/vmd.c
@@ -541,8 +541,23 @@ static void vmd_domain_reset(struct vmd_dev *vmd)
PCI_CLASS_BRIDGE_PCI))
continue;
- memset_io(base + PCI_IO_BASE, 0,
- PCI_ROM_ADDRESS1 - PCI_IO_BASE);
+ /*
+ * Temporarily disable the I/O range before updating
+ * PCI_IO_BASE.
+ */
+ writel(0x0000ffff, base + PCI_IO_BASE_UPPER16);
+ /* Update lower 16 bits of I/O base/limit */
+ writew(0x00f0, base + PCI_IO_BASE);
+ /* Update upper 16 bits of I/O base/limit */
+ writel(0, base + PCI_IO_BASE_UPPER16);
+
+ /* MMIO Base/Limit */
+ writel(0x0000fff0, base + PCI_MEMORY_BASE);
+
+ /* Prefetchable MMIO Base/Limit */
+ writel(0, base + PCI_PREF_LIMIT_UPPER32);
+ writel(0x0000fff0, base + PCI_PREF_MEMORY_BASE);
+ writel(0xffffffff, base + PCI_PREF_BASE_UPPER32);
}
}
}