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authorKishon Vijay Abraham I <kishon@ti.com>2017-08-18 16:58:03 +0200
committerBjorn Helgaas <bhelgaas@google.com>2017-08-29 23:00:39 +0200
commit85aa13997444d7ac83da4094be513ad3fa2384b1 (patch)
tree2b69636e1e5ae8a4c6b7290fcc3a610220bd8270 /drivers/pci/dwc/pci-dra7xx.c
parentPCI: dwc: designware: Provide page_size to pci_epc_mem (diff)
downloadlinux-85aa13997444d7ac83da4094be513ad3fa2384b1.tar.xz
linux-85aa13997444d7ac83da4094be513ad3fa2384b1.zip
PCI: dra7xx: Reset all BARs during initialization
dra7xx has all base address registers (BAR) enabled by default. Reset all BARs during initialization and so that BARs are enabled only if they are actually used. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/dwc/pci-dra7xx.c')
-rw-r--r--drivers/pci/dwc/pci-dra7xx.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index f2fc5f47064e..ee61f833b62c 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -335,10 +335,23 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
+static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+ u32 reg;
+
+ reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+ dw_pcie_writel_dbi2(pci, reg, 0x0);
+ dw_pcie_writel_dbi(pci, reg, 0x0);
+}
+
static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+ enum pci_barno bar;
+
+ for (bar = BAR_0; bar <= BAR_5; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
}