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author | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-06 20:36:56 +0200 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-10-12 05:56:46 +0200 |
commit | 5649e4ced9671e01bdb1f50b2b5987d44c9a6d3d (patch) | |
tree | d3b35795070910b180c0aa06242ed8b322a04b6b /drivers/pci/host/pci-keystone-dw.c | |
parent | PCI: keystone: Use generic DesignWare accessors (diff) | |
download | linux-5649e4ced9671e01bdb1f50b2b5987d44c9a6d3d.tar.xz linux-5649e4ced9671e01bdb1f50b2b5987d44c9a6d3d.zip |
PCI: keystone: Pass keystone_pcie, not address, to IRQ functions
Instead of passing the application register base to IRQ functions,
pass the struct keystone_pcie. This will allow them to use register
accessors. No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host/pci-keystone-dw.c')
-rw-r--r-- | drivers/pci/host/pci-keystone-dw.c | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/drivers/pci/host/pci-keystone-dw.c b/drivers/pci/host/pci-keystone-dw.c index ce97816f5d64..dae68a230440 100644 --- a/drivers/pci/host/pci-keystone-dw.c +++ b/drivers/pci/host/pci-keystone-dw.c @@ -261,25 +261,26 @@ void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) writel(offset, ks_pcie->va_app_base + IRQ_EOI); } -void ks_dw_pcie_enable_error_irq(void __iomem *reg_base) +void ks_dw_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { - writel(ERR_IRQ_ALL, reg_base + ERR_IRQ_ENABLE_SET); + writel(ERR_IRQ_ALL, ks_pcie->va_app_base + ERR_IRQ_ENABLE_SET); } -irqreturn_t ks_dw_pcie_handle_error_irq(struct device *dev, - void __iomem *reg_base) +irqreturn_t ks_dw_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) { u32 status; - status = readl(reg_base + ERR_IRQ_STATUS_RAW) & ERR_IRQ_ALL; + status = readl(ks_pcie->va_app_base + ERR_IRQ_STATUS_RAW) & + ERR_IRQ_ALL; if (!status) return IRQ_NONE; if (status & ERR_FATAL_IRQ) - dev_err(dev, "fatal error (status %#010x)\n", status); + dev_err(ks_pcie->pp.dev, "fatal error (status %#010x)\n", + status); /* Ack the IRQ; status bits are RW1C */ - writel(status, reg_base + ERR_IRQ_STATUS); + writel(status, ks_pcie->va_app_base + ERR_IRQ_STATUS); return IRQ_HANDLED; } |