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authorBjorn Helgaas <bhelgaas@google.com>2016-10-06 20:25:46 +0200
committerBjorn Helgaas <bhelgaas@google.com>2016-10-11 15:30:33 +0200
commitad8802189426cf7b3a2ad0444f71981fb81312a8 (patch)
tree524f4559a9f5c984a31bb977f5ab9e384586d57c /drivers/pci/host/pcie-designware.h
parentPCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces (diff)
downloadlinux-ad8802189426cf7b3a2ad0444f71981fb81312a8.tar.xz
linux-ad8802189426cf7b3a2ad0444f71981fb81312a8.zip
PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments
Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/host/pcie-designware.h')
-rw-r--r--drivers/pci/host/pcie-designware.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index 60cbc682618f..c41384832766 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -55,7 +55,7 @@ struct pcie_port {
struct pcie_host_ops {
u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
- void (*writel_rc)(struct pcie_port *pp, u32 val, u32 reg);
+ void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val);
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,